Using Make

The "make" command allows easy maintenance of large programs. To avoid recompiling the complete program every time a minor change is made, the program is broken up into modules with dependencies between these modules. A file named "makefile" is used as an implicit argument to the "make" command. This file specifies the dependencies that exist between the modules. When the make command is invoked, the system will check out the dependencies and if a dependent file has been modified, the specified command(s) will be executed. There exists a built-in dependency between .c (c source) and .o (object module) files. For example, the following lines specify the dependency of module1.o on the file dec.c and module1.c. Actually, module1.c is not necessary since there is an implicit dependency. 

module1.o: dec.c module1.c 
	gcc -c module1.c
If dec.c or module1.c is modified, make will invoke the command found on the second line ( a tab character must preceed the command) causing a recompilation of module1.c to produce module1.o. The -c option tells gcc to create an object file, not an executable file. If make is invoked and none of the files have been modified since the last compilation of module1.c, then no action is required; i.e. recompilation is not necessary.

A final executable file can be produced by specifying a dependency on the appropriate object modules as illustrated by the following two lines: 
asm: pass1.o pass2.o 
	gcc -o asm pass1.o pass2.o

The -o option says to combine all .o files into an executable called asm in this case. The executable file name asm immediately follows the -o flag and the object files to be linked complete the line.

Here are two examples where makeex1.tar.gz is a simple introduction to make files contained in a single directory and makeex2.tar.gz is a more complicated example using multiple directories.